AMD or Intel as well as the memory brand - page 38

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benik >> :
I'll get into debt and buy myself an Xeon W5590.

Take your time. Intel seems to be releasing Nehalem on 775 socket.

There were a lot of tests & CPU-Z screenshots here, but didn't see any mention that Intel with hyper threading enabled cuts the cache in half between 2 "virtual" CPUs.

For pure experimentation I recommend to turn HT off (and thus increase core performance for 1 thread)

 

 

Who's wondering about hyper-trading.

Turned it off... used to be 64.5 sec (table anl 28 page has it)


 
Without HT in the Expert Advisor for some reason it says initially that to wait 1.5 hours is nonsense.... ok, maybe something with the history or settings is wrong then I will quit
 

Не торопись. Intel похоже выпустит Nehalem на 775 сокет

JavaDev, if you don't know anything about the subject, you shouldn't write such nonsense!

 
Docent >> :

JavaDev, if you don't know anything about the subject, you shouldn't write such nonsense!

If you are knowledgeable in the matter, then write why it's rubbish!

 
JavaDev >> :

Take your time. Intel seems to be releasing Nehalem on 775 socket.

There were a lot of tests & CPU-Z screenshots here, but didn't see any mention that Intel with hyper threading enabled cuts the cache in half between 2 "virtual" CPUs.

For pure experimentation I recommend to disable HT (and thus increase core performance for 1 thread).

It's hard to see anything here - there have been mentions. Your humble servant in particular advised to turn this mode off, commenting on a test where it was seen that HT was on. It seems to be for the 4th stump. (By the way. this mode is where Intel first appeared. But that's just for reference). And I'm not the only one...

There is so much written here, it's hard to make sense out of it. It's good, at least the results are tracked.

 

BAGOR

почему это ЧУШЬ??!

Because the move to LGA1366 and 1156 was due to the fact that in CPUs with Nehalem architecture (Bloomfield and Lynnfield cores) the memory controller is integrated inside the chip while in earlier CPUs the memory controller was located in the chipset north bridge. This is not the same as during the transition from Socket 478 to LGA775 when virtually identical processors were available in 2 "form factors". Here you can see absolutely different signals on all pins of the processor. Need I explain further?
 
Docent >> :

JavaDev, if you don't know anything about the subject, you shouldn't write such nonsense!

Funny :)

Download latest InfInstaller for 9xx,3,4 Intel chipset and make sure (but you'll have to dig around in inf files), it's a little unclear what North Bridge they will be compatible with and how the stones themselves will be called (i3/i4). (Well, they will take out the north bridge from the stone, will take it out...)

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